There is a semiconductor device having a relatively deep isolation structure formed therein, to electrically insulate a plurality of semiconductor elements, as a semiconductor device in which a plurality of semiconductor elements, such as high withstand voltage power MOS (Metal Oxide Semiconductor) transistors, are mounted therein. This deep isolation structure is called a DTI (Deep Trench Isolation) structure.
In the DTI structure, an etching process is performed for the semiconductor substrate, with using a hard mask, such as a silicon oxide film, as an etching mask. By so doing, a relatively deep trench with a depth of approximately 1 μm to 10 μm is formed. Next, an insulating film is formed in this trench.
At this time, a thickness of the hard mask formed in the outer circumferential part of the semiconductor substrate is thinner than a thickness of the hard mask formed in the region inside the semiconductor substrate. Then, while performing the etching process, in the outer circumferential part of the semiconductor substrate, the part of the hard mask is removed. This may cause generation of a region in which the semiconductor substrate is exposed.
The exposed region of the semiconductor substrate is continuously etched, until the trench is formed. Thus, in the outer circumferential part of the semiconductor substrate, a level difference is generated between the region in which the semiconductor substrate is etched and the region in which the semiconductor substrate is not etched. The semiconductor substrate having the trench formed therein is transported for the next process. Then, a predetermined process is performed for the semiconductor substrate by a predetermined semiconductor manufacturing device.
When a process is performed for the semiconductor substrate in the semiconductor manufacturing device, the semiconductor substrate is held by a predetermined holding member. When the semiconductor substrate is transported, the semiconductor substrate is also held by a predetermined holding member. This holding member includes a holding member in a mode of simply pinching the outer circumferential part of the semiconductor substrate. It also includes a holding member in a mode of rotating in a state where the outer circumferential part of the semiconductor substrate is pinched.
Particularly, in a process after the DTI structure is formed, in a mode where a level difference is generated in the outer circumferential part of the semiconductor substrate, the outer circumferential part is pinched by the holding member. At this time, the holding member interferes with the level difference generated in the outer circumferential part of the semiconductor substrate. This may result in chipping a part of the semiconductor substrate. In addition, the semiconductor substrate may be broken.
To solve these problems, various proposals have been made. For example, Japanese Unexamined Patent Application Publication No. 2005-277050 proposes a technique for reducing a level difference by performing a polishing process for the level difference generated in the outer circumferential part of the semiconductor substrate. Japanese Unexamined Patent Application Publication No. 2011-61066 proposes a technique for avoiding etching of the outer circumferential part, by additionally forming a protective film covering the outer circumferential part of the semiconductor substrate and performing an etching process at the time of forming a trench. Japanese Unexamined Patent Application Publication No. 2011-61066 proposes also a technique for attaching a clamp to the outer circumferential part, to avoid etching of the outer circumferential part due to the etching process at the time of forming the trench.